1. Field of the Invention
The present invention relates to a computer system equipped with a cache memory interposed between a processor and a main memory. More specifically, the present invention relates to a computer system that uses access requests from the processor to the main memory and variables set up beforehand to automatically generate and issue pre-fetch requests.
2. Description of Related Technology
In computer systems equipped with a cache to offset performance differences between a processor and main memory, latency from data reads are reduced by using a pre-fetch request before a data read request is received from the processor, thus allowing data that may be used in the future to be read into cache memory from the main memory beforehand. For example, in Japanese laid-open patent publication number 62-192831, a processor issues a pre-fetch request at the same time that it issues a memory access request. On the cache memory side, the pre-fetch request is received and, if the memory access request misses the cache, the requested block and the next block are loaded from main memory into the cache memory.
FIG. 4 shows a schematic block diagram of a computer system equipped with a cache controller. FIG. 4 shows a processor 201, a cache controller 202, a main memory 205, and a cache memory 206. The cache controller 202 includes a pre-fetch controller 203 that generates pre-fetch requests and a cache controller 204 that reads data from the cache memory 206 and the main memory 205.
The pre-fetch controller 203 includes: an address register that latches an address output from the processor 201 via a path 250; a line size register 207 that stores the line width (block width) of the cache: an adder 208 that adds the address received from the address register 209 via a path 256 and a line size received from the line-size register 207 via a path 251; a transaction selector 210 that uses a select signal received via a path 257 to select between addresses received from the path 256 and the path 252, and that issues the selected address to the processor 201 via the path 250; and a controller 211 that receives access requests from the processor 201 via the path 250 and that generates a select signal for the transaction selector 210.
The following is a description of the operations performed by the cache controller 202. The processor 201 issues a data read request and a pre-fetch request to the cache controller 202 via the path 250. In the pre-fetch controller 203 of the cache controller 202, the controller 211 receives the requests from the processor 201, and the address is set up in the address register 209. The controller 211 first generates a select signal via the path 257 so that the address from the address register 209 is selected as the output from the transaction selector 210. The transaction selector 210 selects the data read address from the address register 209 and sends this to the cache controller 204 via the path 253. At the same time, the controller 211 issues a data read request to the cache controller 204 via the path 254. The cache controller 204 determines if the data corresponding to the read request is already stored in the cache memory 206. If it is, the data is read from the cache memory 206 via the path 258 and is then sent to the processor 201 via the path 259. The cache controller 204 then notifies the controller 211 via the path 254 that the data read is completed, and the operation is terminated.
If the data corresponding to the read request is not stored in the cache memory 206, the cache controller 204 reads data from the main memory 205 via the path 257 and writes this data to the cache memory 206 via the path 258. At the same time, this read data from the main memory 205 is sent to the processor 201 via the path 259. The cache controller 204 then notifies the controller 211 via the path 254 that the data read operation has been completed. The controller 211 performs data communication control with the processor 201 via the path 255. At this point, the controller 211 sends a select signal to the transaction selector 210 via the path 257 so that the next pre-fetch address is selected. The transaction selector 210 selects the address (pre-fetch address) from the adder 208 and outputs this to the cache controller 204 via the path 253. At the same time, the controller 211 issues a request to read pre-fetch data from the main memory 205 to the cache controller 204 via the path 254. The cache controller 204 reads, via the path 257, the next data after the data corresponding to the previous read request from the main memory 257. This data is written to the cache memory 206 via the path 258. When this is completed, the cache controller 204 notifies the controller 211 that the data read operation has been completed. The controller 211 notifies the processor 201 via the path 255 that the pre-fetch operation has been completed. In the conventional technology described above, if there is a pre-fetch request from the processor, the data read into the cache memory includes only two lines of data, assuming a cache miss: the data requested by the processor and the subsequent data. Pre-fetching data other than these two lines of data would require the processor to frequently issue repeated pre-fetch requests.
Furthermore, if the processor is not equipped with the feature for issuing pre-fetch requests, pre-fetches are not generated since the cache controller itself does not generate pre-fetch requests. This prevents effective use of the cache memory. Also, even if the data requested by the processor generates a cache hit, the next data will not necessarily generate a cache hit. However, in the conventional technology described above, if data requested from the processor generates a cache hit, the pre-fetch request from the processor is ignored. This also prevents effective use of the cache memory.
The object of the present invention is to overcome the problems of the conventional technology described above and to allow cache memory to be used effectively in the following manner; when a read access request for main memory is issued by a processor, a cache controller generates at least one pre-fetch request with a variable stride width or with an address that is higher or lower than the requested address. This allows more data to be written to the cache memory, thus allowing effective use of the cache memory.
In the present invention, a cache controller includes: means for storing variables, including a pre-fetch block size and a stride value; means for generating at least one pre-fetch request based on an access request for the main memory from the processor and the variables; and means for reading data from the main memory based on the generated pre-fetch request and writing the data to the cache memory.
Also, the cache controller generates pre-fetch requests with addresses that are either higher or lower than the address of the main memory access request. To eliminate excess requests for the main memory, the cache controller suppresses pre-fetch requests if a cache hit is generated by the generated pre-fetch request.